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25 mhz direct digital synthesizer, waveform generator data sheet ad9832 rev. e document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for i ts use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devic es. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 1999 C 2013 analog devices, inc. all rights reserved . technical support www.analog.com features 25 mhz speed on - c hip s in look up table on - c hip , 10 - b it dac serial l oading power - down option t emperature range: ?40 c to +85 c 200 mw power consumption 16- lead tssop applications frequency stimulus/waveform generation frequency phase tuning and mod ulation low power rf/communications systems liquid and gas flow measurement sensory applications: proximity, motion, and defect detection test and medical equipment general description the ad9832 is a numerically controlled oscillator employing a phase accumulator, a sine look - up table , and a 10 - bit digital - to - analog converter (dac) integrated on a single cmos chip. modulation capabilities are provided for phase modulation and frequency modulation. clock rates up to 25 mhz are supported. frequency accura cy can be controlled to one part in 4 billion. modulation is effected by loading registers through the serial interface. a power - down bit allows the user to power down the ad9832 when it is not in use, the power consumption being reduced to 5 mw (5 v) or 3 mw (3 v). the part is available in a 16 - lead tssop package. similar dds products can be found at www.analog.com/dds . functional block dia gram iout comp refin fs adjust refout agnd avdd dgnd dvdd mclk psel 0 psel 1 1 2 ad983 2 on-board reference 10-bit dac phase0 reg phase1 reg phase2 reg phase3 reg full-scale control si n r o m phas e accumulato r ( 32 b it ) freq0 reg freq1 reg 16-bit data register sync fselect fselect bit selsrc sync 8 lsbs 8 msbs decode logic fsync sclk sdata serial register control register fselect/psel register defer register sync sync selsrc psel0 bit psel1 bit mux mux mux mux mux 09090-001 figure 1.
ad9832 data sheet rev. e | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 functional block diagram .............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing characteristics ................................................................ 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 terminology .................................................................................... 11 theory of operation ...................................................................... 12 circuit description ......................................................................... 13 numerical contr olled oscillator and phase modulator ....... 13 sine look - up table (lut) ........................................................ 13 digital - to - analog converter .................................................... 13 functional description .................................................................. 14 serial interface ............................................................................ 14 direct data transfer and deferred data transfer ................. 14 latency ......................................................................................... 16 flowcharts ................................................................................... 16 applications information .............................................................. 19 grounding and layout .............................................................. 19 interfacing the ad9832 to microprocessors .............................. 19 ad 9832 to adsp - 2101 interface ............................................. 19 ad9832 to 68hc11/68l11 interface ....................................... 20 ad9832 to 80c51/80l51 interface .......................................... 20 ad9832 to dsp56002 interface ............................................... 20 evaluation board ............................................................................ 21 system demonstration platform .............................................. 21 ad9832 to sport interface ..................................................... 21 xo vs. external clock ................................................................ 21 power supply ............................................................................... 21 evaluation board schematics ................................................... 22 evaluation board layout ........................................................... 24 order ing information .................................................................... 25 bill of materials ........................................................................... 25 outline dimensions ....................................................................... 26 or dering guide .......................................................................... 26 revision history 2/13 rev. d to rev. e changes to table 10 ........................................................................ 15 changes to flowcharts section ..................................................... 16 7 /12 rev. c to rev. d changed on - chip co s look up table to on - chip s in look up table in features section ................................................................. 1 9/1 1 rev. b to rev. c changes to features and applications ........................................... 1 changes to specification statement ............................................... 3 changes to timing characteristics statement ............................. 5 replaced evaluation board section; renumbered sequentially ..................................................................................... 21 changes to ordering guide .......................................................... 26 6 /10 rev. a to rev. b updated format .................................................................. universal changed cmos complete dds to 3 v to 5.0 v programmable waveform generator ......................................................................... 1 changes to serial interface section .............................................. 14 updated outline dimensions ....................................................... 23 changes to ordering guide .......................................................... 23 7/99 rev 0 to rev. a
data sheet ad9832 rev. e | pa ge 3 of 28 specifications v dd = +5 v 5%; agnd = dgnd = 0 v; t a = t min to t max ; refin = refout; r set = 3.9 k?; r load = 300 ? for iout, unless otherwise noted. also, see figure 2 . table 1 . parameter 1 ad9832b unit test conditions/comments signal dac specifications resolution 10 bits update rate (f max ) 25 msps nom iout full scale 4 ma nom 4.5 ma max output compliance 1.35 v max 3 v power supply dc accuracy integral nonlinearity 1 lsb typ differential nonlinearity 0.5 lsb typ dds specifications 2 dynamic specifications si gnal -to - noise ratio 50 db min f mclk = 25 mhz, f out = 1 mhz total harmonic distortion ? 53 dbc max f mclk = 25 mhz, f out = 1 mhz spurious - free dynamic range (sfdr) 3 f mclk = 6.25 mhz, f out = 2.11 mhz narrow band ( 50 khz) ? 72 dbc min 5 v power supply ? 70 dbc min 3 v power supply wide b and ( 2 mhz) ? 50 dbc min clock feedthrough ? 60 dbc typ wake - up time 4 1 ms typ power - down option yes v o ltage reference internal reference @ 25 c 1.21 v typ t min to t max 1.21 7% v min/ v max refin input impedance 10 m ? typ reference t emperature coefficient (tc) 100 ppm/ c typ refout outpu t impedance 300 ? typ logic inputs input high voltage , v inh v dd ? 0.9 v min input low voltage , v inl 0.9 v max input current , i inh 10 a max input capacitance , c in 10 pf max power supplies avdd 2.97/5.5 v min/v max dvdd 2.97/5. 5 v min/v max i aa 5 ma max 5 v power supply i dd 2.5 + 0.4/mhz ma typ 5 v power supply i aa + i dd 5 15 ma max 3 v power supply 24 ma max 5 v power supply low power sleep mode 350 a max 1 operating temperature range is ? 40 c to +85 c. 2 100% production tested. 3 f mclk = 6.25 mhz, frequency word = 0x 5671c71c, and f out = 2.11 mhz. 4 se e figure 13 . to reduce the wake- up time at low power supplies and low temperature, the use of an external reference is suggested. 5 measured with the digital inputs static and equal to 0 v or dvdd. the ad9832 is tested w ith a capa citive load of 50 pf. the part can operate with higher capacitive loads, but the magnitude of the analog output will be attenuated. for example, a 5 mhz output signal is attenuated by 3 db when the load capacitance equals 85 pf.
ad9832 data sheet rev. e | page 4 of 28 iout comp refin fs adjust refout 12 ad9832 on-board reference 10-bit dac sin rom full-scale control 300? 50pf r set 3.9k? 10nf 10nf avdd 09090-002 figure 2 . test circuit by which spe cifications were tested
data sheet ad9832 rev. e | pa ge 5 of 28 t iming c haracteristics v dd = +5 v 5%; agnd = dgnd = 0 v, unless otherwise noted. table 2 . parameter limit at t min to t max (b version) unit test conditions/comments t 1 40 ns min mclk p eriod t 2 16 ns min mclk high duration t 3 16 ns min mclk low duration t 4 50 ns min sclk p eriod t 5 20 ns min sclk high duration t 6 20 ns min sclk low duration t 7 15 ns min fsync to sclk falling edge setup time t 8 20 ns min fsync to sclk hold time sclk ? 5 ns max t 9 15 ns min data setup time t 10 5 ns min data hold time t 11 8 ns min fselect, psel0, psel1 setup time before mclk rising edge t 11a 1 8 ns min fselect, psel0, psel1 setup time after mclk rising edge 1 see the pin configuration and function descriptions section . timing diagrams mclk t 2 t 1 t 3 09090-003 fig ure 3 . master clock sclk fsync sdata t 5 t 4 t 6 t 7 t 8 t 10 t 9 d14 d15 d0 d1 d2 d15 d14 09090-004 figure 4 . serial timing t 11a t 11 valid data valid data valid data mclk fselect psel0, psel1 09090-005 figure 5 . control timing
ad9832 data sheet rev. e | page 6 of 28 absolute maximum rat ings t a = 25 c , unless otherwise noted . table 3 . parameter r ating avdd to agnd ? 0.3 v to +7 v dvdd to dgnd ? 0.3 v to +7 v avdd to dvdd ? 0.3 v to +0.3 v agnd to dgnd ? 0.3 v to +0.3 v digital i/o voltage to dgnd ? 0.3 v to dvdd + 0.3 v analog i/o voltage to agnd ? 0.3 v to avdd + 0.3 v operating temperature range industrial (b ve rsion) ? 40 c to +85 c storage temperature range ? 65 c to +150 c maximum junction temperature 150 c tssop ja thermal impedance 158 c/w lead temperature, soldering vapor phase (60 sec) 215 c infrared (15 sec) 220 c esd rating >4500 v stresses abo ve those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specificatio n is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
data sheet ad9832 rev. e | pa ge 7 of 28 pin configuration an d function descripti ons fs adjust agnd iout avdd comp refin refout dvdd fselect psel1 psel0 dgnd mclk sclk sdata fsync 1 2 3 4 5 6 7 8 16 15 14 13 12 1 1 10 9 ad9832 t op view (not to scale) 09090-006 figure 6. pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 fs adjust full - scale adjust control. a resistor (r set ) is connected between this pin and agnd. this determines the magnitude of the full - scale dac current. the relationship between r set and the full - scale current is iout full - scale = 12.5 v refin /r set , where v refin = 1.21 v nominal and r set = 3.9 k ? t ypical . 2 refin voltage reference input. the ad9832 can be used with either the on - board reference, which is available from the refout pin , or an external reference. the reference to be used is connected to the refin pin. the ad9832 accepts a referenc e of 1.21 v nominal. 3 refout voltage reference output. the ad9832 has an on - board reference of value 1.21 v nominal. the reference is available on the refout pin. this reference is used as the reference to the dac by connecting refout to refin. refout should be decoupled with a 10 nf capacitor to agnd. 4 dvdd positive power supply for the digital section. a 0.1 f decoupling capacitor should be connected between dvdd and dgnd. dvdd can have a value of 5 v 10% or 3.3 v 0%. 5 dgnd digital ground. 6 mclk digital clock input. dds output frequencies are expressed as a binary fraction of the frequency of mclk. this clock determines t he output frequency accuracy and phase noise. 7 sclk serial clock, logic input. data is clocked into the ad9832 on each falling sclk edge. 8 sdata serial data in, logi c input. the 16 - bit serial data - word is applied to this input. 9 fsync data synchronization signal, logic input. when this input goes low, the internal logic is informed that a new word is being loaded into the device. 10 fselect frequency select input. fselect controls which frequency register, freq0 or freq1, is used in the phase accumulator. the frequency register to be used can be selected using the fselect pin or the fselect bit . fselect is sampled on the rising mclk edge. fselect needs to be in steady state when an mclk rising edge occurs. if fselect changes value when a rising edge occurs, there is an uncertainty of one mclk cycle as to when control is transferred to the other frequency register. to avoid any uncertainty, a change on fselect should not coincide with an mclk rising edge. when the bit is being used to select the frequency register, the fselect pin should be tied to dgnd. 11, 12 psel1, psel0 phase select input. the ad9832 has four phas e registers. these registers can be used to alter the value being input to the sin rom. the contents of the phase register are added to the phase accumulator output, the inputs psel0 and psel1 selecting the phase register to be used. alternatively, the p hase register to be used can be selected using the psel0 and psel1 bits . like the fselect input, psel0 and psel1 are sampled on the rising mclk edge. therefore, these inputs need to be in steady state when an mclk rising edge occurs or there is an uncer tainty of one mclk cycle as to when control is transferred to the selected phase register. when the phase registers are being controlled by the psel0 and psel1 bits , the pins should be tied to dgnd. 13 agnd analog ground. 14 iout current output. this is a high impedance current source. a load resistor should be connected between iout and agnd. 15 avdd positive power supply for the analog section. a 0.1 f decoupling capacitor should be connected between avdd and agnd. avdd can have a value of 5 v 10% or 3.3 v 10%. 16 comp compensation p in. this is a compensation pin for the internal reference amplifier. a 10 nf decoupling ceramic capacitor should be connected between comp and avdd.
ad9832 data sheet rev. e | page 8 of 28 typical performance characteristics mclk frequenc y (mhz) t ot al current (ma) 25 20 0 25 10 5 15 20 15 10 5 5v 3.3 v t a = 2 5 c 09090-007 figure 7 . typical current consumption vs. mclk frequency mclk frequenc y (mhz) 25 10 15 20 sfdr ( 50khz) (db) ?50 ?55 ?80 ?60 ?65 ?75 ?70 f out /f mclk = 1/3 avdd = dvdd = 3.3v 09090-008 figure 8. narrow - band sfdr vs. mclk frequency mclk frequenc y (mhz) 25 10 15 20 sfdr (2mhz) (db) ?40 ?45 ?65 ?50 ?55 ?60 f out /f mclk = 1/3 avdd = dvdd = 3.3v 09090-009 figure 9 . wideb and sfdr vs. mclk frequency 10mhz ?40 ?45 ?80 0.4 0.1 0 0.2 0.3 ?60 ?65 ?70 ?75 ?50 ?55 avdd = dvdd = 3.3v 25mhz sfdr (2mhz) (db) f out / f mclk 09090-010 figure 10 . wideb and sf dr vs. f out / f mclk for various mclk frequencies mclk frequenc y (mhz) snr (db) 60 55 40 25 15 10 20 50 45 avdd = dvdd = 3.3v f out = f mclk /3 09090-0 1 1 figure 11 . snr vs. mclk frequency 10mhz 25mhz snr (db) 60 55 40 50 45 avdd = dvdd = 3.3v f out / f mclk 0.4 0.3 0.2 0.1 0 09090-012 figure 12 . snr vs. f out /f mclk for various mclk frequencies
data sheet ad9832 rev. e | pa ge 9 of 28 temper a ture (c) w ake-u p time (ms) 10.0 7.5 0 0 ?30 ?40 ?20 ?10 5.0 2.5 avdd = dvdd = 2.97v 09090-013 figure 13 . wake - up time vs. t emperature vbw 1khz 10db/div 0 ?70 ?100 start 0hz rbw 300hz stop 12.5mhz st 277 sec ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 09090-014 figure 14 . f mclk = 25 mhz, f out = 1.1 mhz, frequency word = 0x b439581 vbw 1khz 10db/div 0 ?70 ?100 start 0hz rbw 300hz stop 12.5mhz st 277 sec ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 09090-015 figure 15 . f mclk = 25 mhz, f out = 2.1 mhz, frequency word = 0x 15810625 vbw 1khz 10db/div 0 ?70 ?100 start 0hz rbw 300hz stop 12.5mhz st 277 sec ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 09090-016 figure 16 . f mclk = 25 mhz, f out = 3.1 mhz, frequency word = 0x 1fbe76c9 vbw 1khz 10db/div 0 ?70 ?100 start 0hz rbw 300hz stop 12.5mhz st 277 sec ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 09090-017 figure 17 . f mclk = 25 mhz, f out = 4.1 mhz, frequency word = 0x 29fbe76d vbw 1khz 10db/div 0 ?70 ?100 start 0hz rbw 300hz stop 12.5mhz st 277 sec ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 09090-018 figure 18 . f mclk = 25 mhz, f out = 5.1 mhz, frequency word = 0x 34395810
ad9832 data sheet rev. e | page 10 of 2 8 vbw 1khz 10db/div 0 ?70 ?100 start 0hz rbw 300hz stop 12.5mhz st 277 sec ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 09090-019 figure 19 . f mclk = 25 mhz, f out = 6.1 mhz, frequency word = 0x 3e76c8b4 vbw 1khz 10db/div 0 ?70 ?100 start 0hz rbw 300hz stop 12.5mhz st 277 sec ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 09090-020 figure 20 . f mclk = 25 mhz, f out = 7.1 mhz, frequency word = 0x 48b43958 vbw 1khz 10db/div 0 ?70 ?100 start 0hz rbw 300hz stop 12.5mhz st 277 sec ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 09090-021 figure 21 . f mclk = 25 mhz, f o ut = 8.1 mhz, frequency word = 0x 52f1a9fc vbw 1khz 10db/div 0 ?70 ?100 start 0hz rbw 300hz stop 12.5mhz st 277 sec ?10 ?60 ?80 ?90 ?40 ?50 ?20 ?30 09090-022 figure 22 . f mclk = 25 mhz, f out = 9.1 mhz, frequency word = 0x 5d2f1aa0
data sheet ad9832 rev. e | pa ge 11 of 28 terminology integral nonlinearity this is the maximum deviation of any code from a straight line passing th rough the endpoints of the transfer function. the endpoints of the transfer function are zero scale, a point 0.5 lsb below the first code transition (000 . . . 00 to 000 . . . 01) and full scale, a point 0.5 lsb above the last code transition (111 . . . 10 to 111 . . . 11). the error is expressed in lsbs. differential nonlinearity this is the difference between the measured and ideal 1 lsb change between two adjacent codes in the dac. signal -to - noise - and - distortion ratio it is measured signal to noise at th e output of the dac. the signal is the rms magnitude of the fundamental. noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (f mclk /2) but excluding the dc component. the s ignal - to - noise - and - distortion ratio is dependen t on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal - to - noise - and - distortion ratio for a sine wave input is signal - to - noise - and - d istortion = (6.02n + 1.76 ) db where n is the number of bits. thus, for an ideal 10 - bit converter, the signal - to - noise - and - distortion ratio = 61.96 db. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the rms value of the fundamental. for the ad9832 , thd i s defined as 1 2 6 2 5 2 4 2 3 2 2 log 20 v v v v v v thd + + + + = where: v 1 is the rms amplitude of the fundamental . v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonic. output compliance the output compliance refers to the maximum voltage that can be generated at the output of the dac to meet the specifications . when voltages greater than those specified for the output compliance are generated, the ad9832 may not meet the specifications listed in the data sheet. spurious - free dynamic range (sfdr) a long with the frequency of interest, harmonics of the fundamental frequency and images of the mclk frequency are present at the output of a dds device. sfdr refers to the largest spur or harmonic present in the band of interest. the wide - band sfdr gives th e magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the bandwidth 2 mhz about the fundamental frequency. the narrow band sfdr gives the attenuation of the largest spur or harmonic in a bandwidth of 50 khz about the fundamental frequency. clock feedthrough there is feedthrough from the mclk input to the analog output. clock feedthrough refers to the magnitude of the mclk signal relative to the fundamental frequency in the output spectrum of the ad9832 .
ad9832 data sheet rev. e | page 12 of 28 theory of operation sine waves are typically thought of in terms of their magnitude form a(t) = sin (t). however, these are nonlinear and not easy to generate except through piecewise construction. on the other hand, the angular information is linear in nature. that is, the phase angle rotates through a fixed angle for each unit of time. the angular rate depends on the frequency of the signal by the traditional rate of = 2 f. magnitude phase +1 0 ?1 2 0 09090-023 figure 23 . sine wave knowing that the phase of a s ine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined by phase = ?t solving for , = phase/ t = 2 f solving for f and substituting the reference clock frequency for the reference period (1/f mclk = t) , f = phase f mclk /2 the ad9832 builds the output based on this simple equation. a simple dds chip can implement this equation with three major subcircuits.
data sheet ad9832 rev. e | pa ge 13 of 28 c ircuit d escription the ad9832 provides an exciting new level of integration for the rf/ c ommunications system designer. the ad9832 combines the numerical controlled oscillator (nco), a sine look - up table , frequency and phase modulators, and a dac on a single integrated circuit. the internal circuitry of the ad9832 consists of thr ee main sections. they are: ? numerical controlled oscillator (nco) and phase modulator ? sine look - up table ? dac the ad9832 is a fully integrated direct digital synthesis (dds) chip. the chip requires a reference clock, a low precision resistor , and eight deco upling capacitors to provide digitally created sine waves up to 12.5 mhz. in addition to the generation of this rf signal, the chip is fully capable of a broad range of simple and complex modulation schemes. these modulation schemes are fully implemented i n the digital domain, allowing accurate and simple realization of complex modulation algorithms using dsp techniques. numerical controlled oscillato r and phase modulator the nco and phase modulator consists of two frequency select registers, a phase accumu lator , and four phase offset registers. the main component of the nco is a 32 - bit phase accumulator that assembles the phase component of the output signal. continuous time signals have a phase range of 0 to 2 . outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. the digital implementation is no different. the accumulator simply scales the range of phase numbers into a multibit digital word. the phase accumulator in the ad9832 is implemented with 32 bits. therefore , in the ad9832, 2 = 2 32 . likewise, the phase term is scaled into this range of numbers 0 < phase < 2 32 ? 1. f = phase f mclk /2 32 where 0 < phase < 2 32 . the input to the phase accumulator ( that is , the phase step) can be selected from either the freq0 r egister or th e freq1 r egister and can be controlled by the fselect pin or the fselect bit. ncos inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. following the nco, a phase offset can be added to pe rform phase modulation using the 12 - bit phase x r egisters. the conten ts of th e s e register s are added to the most significant bits of the nco. the ad9832 has four phase x registers, the resolution of these registers being 2 /4096. s ine look - up table (lut) to make the output useful, the signal must be converted from phase information into a sinusoidal value. because phase information maps directly into amplitude, a rom lut converts the phase information into amplitude. to do this, the digital phase information is used to address a sine rom lut. although the nco contains a 32 - bit phase accumulator, the output of the nco is truncated to 12 bits. using the full resolution of the p hase accumulator is impractical and unnecessary b ecause this would require a look - up table of 2 32 entries. it is only necessary to have sufficient phase resolution in the luts s o that the dc error of the output waveform is dominated by the quantization error in the dac. this requires the look - up table to have two more bits of phase resolution than the 10 - bit dac. digital - to - analog converter the ad9832 includes a high impedance current source 10 - bit dac , capable of driving a wide range of loads at different speeds. full - scale output current can be adjusted for optimum power and external load requirements by us ing a single external resistor (r set ). the dac is configured for single - ended operation. the load resistor can be any value required, as long as the full - scale voltage developed across it does not exce ed the voltage compliance range. because full - scale current is controlled by r set , adjustments to r set can balance changes made to the load resistor. however, if the dac full - scale output current is significantly less than 4 ma , the linearity of the dac ma y degrade.
ad9832 data sheet rev. e | page 14 of 28 functional descripti on serial interface the ad9832 has a serial interface, with 16 bits being loaded during each write cycle. sclk, sdata , and fsync are used to load the word into the ad9832. when fsync is taken low, the ad9832 is informed t hat a word is being written to the device. the first bit is read into the device on the next sclk falling edge with the remaining bits being read into the device on the subsequent sclk falling edges. fsync frames the 16 bits ; therefore, when 16 sclk fallin g edges have occurred, fsync should be taken high again. the sclk can be continuous , or alternatively, the sclk can idle high or low between write operations. table 5 . control registers register size description freq0 reg 32 b i ts frequency register 0. this defines the output frequency, when fselect = 0, as a fraction of the mclk frequency. freq1 reg 32 b its frequency register 1. this defines the output frequency, when fselect = 1, as a fraction of the mclk frequency. ph ase0 reg 12 b its phase offset register 0. when psel0 = psel1 = 0, the contents of this register are added to the output of the phase accumulator. phase1 reg 12 b its phase offset register 1. when psel0 = 1 and psel1 = 0, the contents of this regis ter are added to the output of the phase accumulator. phase2 reg 12 b its phase offset register 2. when psel0 = 0 and psel1 = 1, the contents of this register are added to the output of the phase accumulator. phase3 reg 12 b its phase offset regist er 3. when psel0 = psel1 = 1, the contents of this register are added to the output of the phase accumulator. when writing to a frequency/phase register, the first four bits identify whether a frequency or phase register is being written to, the next four bits contain the address of the destination register , while the 8 lsbs contain the data. table 6 lists the addresses for the phase/frequency registers , and table 7 and table 8 list the data structure for each . for an example on programming the ad9832 , see the an - 621 application note , programming the ad9832/ad9835 , at www.analog.com . tab le 6 . addressing the registers a3 a2 a1 a0 destination register 0 0 0 0 freq0 reg 8 l lsbs 0 0 0 1 freq0 reg 8 h lsbs 0 0 1 0 freq0 reg 8 l msbs 0 0 1 1 freq0 reg 8 h msbs 0 1 0 0 freq1 reg 8 l lsbs 0 1 0 1 freq1 reg 8 h lsbs 0 1 1 0 freq1 reg 8 l msbs 0 1 1 1 freq1 reg 8 h msbs 1 0 0 0 phase0 reg 8 lsbs 1 0 0 1 phase0 reg 8 msbs 1 0 1 0 phase1 reg 8 lsbs 1 0 1 1 phase1 reg 8 msbs 1 1 0 0 phase2 reg 8 l sbs 1 1 0 1 phase2 reg 8 msbs 1 1 1 0 phase3 reg 8 lsbs 1 1 1 1 phase3 reg 8 msbs table 7 . 32 - bit frequency word 16 msbs 16 lsbs 8 h msbs 8 l msbs 8 h lsbs 8 l lsbs table 8 . 12 - bit frequency word 4 msbs (the 4 msbs of the 8 - bit word loaded = 0) 8 lsbs direct data transfer and deferred data transfer within the ad9832, 16 - bit transfers are used when loading the destination frequency/phase register. there are two modes for load ing a register , direct data transfer and a deferred data transfer. with a deferred data transfer, the 8 - bit word is loaded into the defer register (8 lsbs or 8 msbs). however, this data is not loade d into the 16 - bit data register; therefore, the destinatio n register is not updated. with a direct data transfer, the 8 - bit word is loaded into the appropriate defer register (8 lsbs or 8 msbs). immediately following the loading of the defer register, the contents of the complete defer register are loaded into th e 16 - bit data register and the destination register is loaded on the next mclk rising edge. when a destination register is addressed, a deferred transfer is needed first followed by a direct transfer. when all 16 bits of the defer register contain relevant data, the destination register can then be updated using 8 - bit loading rather than 16 - bit loading , that is , direct data transfers can be used. for example, after a new 16 - bit word has been loaded to a destination register, the defer register will also con tain this word. if the next write instruction is to the same destination register, the user can use direct data transfers immediately.
data sheet ad9832 rev. e | pa ge 15 of 28 when writing to a phase register, the 4 msbs of the 16 - bit word loaded into the data register should be zero (the phase r egisters are 12 bits wide). to alter the entire contents of a frequency register, four write operations are needed. however, the 16 msbs of a frequency word are contained in a separate register to the 16 lsbs. therefore, the 16 msbs of the frequency word c an be altered independent of the 16 lsbs. table 9 . commands c3 c2 c1 c0 command 0 0 0 0 write 16 phase bits ( p resent 8 b its + 8 b its in the d efer r egister) to s elected phase x reg. 0 0 0 1 write 8 phase bits to the d efer r egister. 0 0 1 0 write 16 frequency bits ( p resent 8 b its + 8 b its in the d efer r egister) to s elected the freq x reg. 0 0 1 1 write 8 frequency bits to the d efer r egister. 0 1 0 0 bit d9 (psel0) and bit d10 (psel1) are used t o s elect the phase x reg when selsrc = 1. when selsrc = 0, the phase x reg is s elected using the psel0 and psel1 pins . 0 1 0 1 bit d11 is used to s elect the freq x reg when selsrc = 1. when selsrc = 0, the freq x reg is s elected using the fselect pin . 0 1 1 0 t o control the psel0, psel1 , and fselect bits using only one write, this command is used. bit d9 and bit d10 are used to s elect the phase x reg , and bit 11 is used to s elect the freq x reg when selsrc = 1. when selsrc = 0, the phase x reg is s elected using the psel0 and psel1 pins and the freq x reg is s elected using the fselect pin . 0 1 1 1 reserved. it c onfigures the ad9832 for test purpose s. the phase and frequency registers to be used are selected using the fselect, psel0 , and psel1 pins, or the cor responding bits can be used. bit selsrc determines whether the bits or the pins are used. when selsrc = 0, the pins are used , and when selsrc = 1, the bits are used. when clr is taken high, selsrc is set to 0 so that the pins are the default source. data t ransfers from the serial (defer) register to the 16 - bit data register , and the fselect and psel registers, occur following the 16th falling sclk edge. table 10 . controlling the ad9832 d15 d14 command 1 0 selects source of c ontrol for the phase x and freq x r egisters and enables s ynchronization. bit d13 is the sync b it. when this bit is h igh, reading of the fselect, psel0 , and psel1 bits/ pins and the loading of the destination register with data is synchronized with the rising edge of mclk. the latency is increased by 2 mclk cycles when sync = 1. when sync = 0, the loading of the data and the sampling of fselect/psel0/psel1 occurs asynchronously. bit d12 is the select source bit (selsrc). when this bit equals 1, the p hasex/freqx reg is selected using the fselect, psel0, and psel1 bits. when selsrc = 0, the phasex/freqx reg is selected using the fselect, psel0, and psel1 pins. 1 1 sleep, reset , and clr (clear) . d13 is the sleep bit. when this bit equals 1, the ad9 832 is powered down, internal clocks are disabled , and the current sources and refout of the dac are turned off. when sleep = 0, the ad9832 is powered up. when reset (d12) = 1, the phase accumulator is set to zero phase that corresponds to a full - scale out put. when clr (d11) = 1, sync and selsrc are set to zero. clr resets to 0 automatically. transfer of the data from the 16 - bit data register to the destination register or from the fselect/psel register to the respective multiplexer occurs on the next mcl k rising edge. because sclk and mclk are asynchronous, an mclk rising edge may occur while the data bits are in a transitional state . this can cause a brief spurious dac output if the register being written to is generating the dac output. to avoid such sp urious outputs, the ad9832 contains synchronizing circuitr y. when the sync bit is set to 1, the synchronizer is enabled and d ata transfers from the serial register (defer register) to the 16 - bit data register , and the fselect/psel registers occur followin g a two - stage pipeline delay that is triggered on the mclk falling edge. the pipeline delay ensures that the data is valid when the transfer occurs. similarly, selection of the frequency/phase registers using the fselect/psel x pins is synchronized with the mclk rising edge when sync = 1. when sync = 0, the synchronizer is bypassed. selecting the frequency/phase registers using the pins is synchronized with mclk internally also when sync = 1 to ensure that these inputs are valid at the mclk rising edge. if t imes t 11 and t 11a are met, then the inputs will be at steady state at the mclk rising edge. however, if times t 11 and t 11a are violated, the internal synchronizing circuitry will delay the instant at which the pins are sampled, ensuring that the inputs are valid at the sampling instant (see figure 5 ) .
ad9832 data sheet rev. e | page 16 of 28 table 11 . writing to the ad9832 data registers d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 c2 c1 c0 a3 a2 a1 a0 msb x 1 x 1 x 1 x 1 x 1 x 1 lsb 1 x = dont care. table 12 . setting sync and selsrc d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 0 sync selsrc x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 1 x = dont care. t able 13 . power - down, resetting and clearing the ad9832 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 1 1 sleep reset clr x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 x 1 1 x = dont care. latency associat ed with each operation is a latency. when inputs fselect/psel change value, there is a pipeline delay before control is transferred to the selected register ; there is a pipeline delay before the analog output is controlled by the selected register. when ti mes t 11 and t 11a are met, psel0, psel1 , and fselect have latencies of six mclk cycles when sync = 0. when sync = 1, the latency is increased to 8 mclk cycles. when times t 11 and t 11a are not met, the latency can increase by one mclk cycle. similarly, there is a latency associated with each write operation. if a selected frequency/phase register is loaded with a new word, there is a delay of 6 to 7 mclk cycles before the analog output will change (there is an uncertainty of one mclk cycle regarding the mclk rising edge at which the data is loaded into the destination register). when sync = 1, the latency is 8 or 9 mclk cycles. flow c harts the flowchart in figure 24 shows the operating routine for the ad9832. whe n the ad9832 is powered up, the part should be reset , which reset s the phase accumulator to zero so that the analog output is at full scale . to avoid spurious dac outputs while the ad9832 is being initialized, the reset bit should be set to 1 until the par t is ready to begin generating an output. taking clr high set s sync and selsrc to 0 so that the fselect/psel x pins are used to select the frequency/phase registers , and the synchronization circuitry is bypassed. a write operation is needed to the sync/sels rc register to enable the synchronization circuitry or to change control to the fselect/ psel bits. reset does not reset the phase and frequency registers. these registers wil l contain invalid data and, therefore, should be set to a known value by the user . the reset bit is then set to 0 to begin generating an output. a signal will appear at the dac output 6 mclk cycles after reset is set to 0. the analog output is f mclk /2 32 freg , where freg is the value loaded into the selected frequency register. this s ignal is phase shifted by the amount specified in the selected phase register (2 /4096 phase x reg , where phase x reg is the value contained in the selected phase register). control of the frequency/phase registers can be interchanged from the pins to the bits.
data sheet ad9832 rev. e | pa ge 17 of 28 select data sources set fselect set psel0, psel1 initialization wait 6 mclk cycles (8 mclk cycles if sync = 1) dac output v out = v refin 6.25 r out /r set (1 + sin(2(freg f mclk t/2 32 + phasereg/2 12 ))) change phase? no change f out ? change f out ? yes no yes no yes change fselect change phasereg? no yes change psel0, psel1 data write freg[0] = f out0 / f mclk 2 32 freg[1] = f out1 / f mclk 2 32 phasereg [3:0] = delta phase[0, 1, 2, 3] 09090-024 figure 24 . flow c hart for the ad9832 initialization and operation initialization control register write set sleep reset = 1 clr = 1 set sync and/or selsrc to 1 yes no control register write sync = 1 and/or selsrc = 1 set pins or frequency/phase register write set fselect, psel0 and psel1 control register write sleep = 0 reset = 0 clr = 0 write initial data freg[0] = f out0 / f mclk 2 32 freg[1] = f out1 / f mclk 2 32 phasereg[3:0] = delta phase[0, 1, 2, 3] 09090-025 figure 25 . initialization
ad9832 data sheet rev. e | page 18 of 28 data write deferred transfer write write 8 bits to defer register direct transfer write write present 8 bits and 8 bits in defer register to data register write another word to this register? write a word to another register change 8 bits only yes no change 16 bits no yes 09090-026 figure 26 . data writes select data sources fselect/psel pins being used? yes selsrc = 0 set pins set fselect set psel0 set psel1 frequency/phase register write set fselect set psel0 set psel1 no selsrc = 1 09090-027 figure 27 . selecting data sources
data sheet ad9832 rev. e | pa ge 19 of 28 applications information the ad9832 contains functions that make it suitable for modulation applications. the part can be used to perform simple modulation , such as fsk, and more complex modulation schemes , such as gmsk and qpsk , can also b e implemented using the ad9832. in an fsk application, the two frequency registers of the ad9832 are loaded with different values; one frequency represent s the space frequency while the other represent s the mark frequency. the digital data stream is fed to the fselect pin, which cause s the ad9832 to modulate the carrier frequency between the two values. the ad9832 has four phase registers; this enables the part to perform psk. with phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount which is related to the bit stream being input to the modulator. the presence of four shift registers eases the interaction needed between the dsp and the ad9832. the ad9832 is also suitable for signal generator applications. with its low current consumption, the part is suitable for applications where it can be used as a local oscillator. in addition, the part is fully specified for operation with a 3.3 v 10% power supply. therefore, in portable applications where current consumption is an important issue, the ad9832 is perfect . grounding and layout the printed circuit board (pcb) that houses the ad9832 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is generally best for ground planes because it gives the best shielding. digital and analog ground planes should only be joined in one place. if the ad9832 is the only device requiring an agnd - to - dgnd connection, the ground planes should be connected at the agnd and dgnd pins of the ad9832. if the ad9832 is in a system where multiple devices require agnd - to - dgnd connections, the connection should be made at one point only, a st ar ground point that should be established as close as possible to the ad9832. avoid running digital lines under the device as these couple noise onto the die. the analog ground plane should be allowed to run under the ad9832 to avoid noise coupling. the p ower supply lines to the ad9832 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals , such as clocks , should be shielded with digital ground to avoid radi ating noise to other sections of the board. avoid crossover of digital and analog signals. traces on opposite sides of the board should run at right angles to each other , which reduce s the effects of feedthrough through the board. a microstrip technique is by far the best , but it is not always possible with a double - sided board. in this technique, the component side of the board is dedicated to ground planes , while signals are placed on the other side. good decoupling is important. the analog and digital s upplies to the ad9832 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. all analog and digital supplies should be decoupled to agnd and dgnd , respectively , with 0.1 f ceramic capacitors in pa rallel with 10 f tantalum capacitors. to achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. in systems where a common supply is used to drive both the avdd and dv dd of the ad9832, it is recommended that the av dd supply of the system be used. this supply should have the recommended analog supply decoupling between the avdd pins of the ad9832 and agnd and the recommended digital supply decoupling capacitors between t he dvdd pins and dg nd. interfacing the ad98 32 to microprocessor s the ad9832 has a standard serial interface that allows the part to interface directly with several microprocessors. the device uses an external serial clock to write the data/control informat ion into the device. the serial clock can have a frequency of 20 mhz maximum. the serial clock can be continuous, or it can idle high or low between write operations. when data/control information is being written to the ad9832, fsync is taken low and held low while the 16 bits of data are being written into the ad9832. the fsync signal frames the 16 bits of information being loaded into the ad9832. ad9832 to adsp - 21 01 interface figure 28 shows the serial interface between the ad98 32 and the adsp - 2101 . the adsp - 2101 should be set up to operate in sport transmit alternate framing mode (tfsw = 1). the adsp - 2101 is programmed through the sport control register and should be configured as follows: internal clock operation (isclk = 1), active low framing (invtfs = 1), 16 - bit word length (slen = 15), internal frame sync signal (itfs = 1), and a frame sync for each write operation (tfsr = 1) must be generate d . transmission is initiated by writing a word to the tx register after sport is enabled. the data is clocked out on each rising edge of the serial clock and clocked into the ad9832 on the sclk falling edge. ad9832* fsync sdata sclk adsp-2101* tfs dt sclk *additional pins omitted for clarity. 09090-028 figure 28 . adsp - 2101 to ad9832 interface
ad9832 data sheet rev. e | page 20 of 28 ad9832 to 68hc11/68l 11 interface fi gure 29 shows the serial interface between the ad9832 and the 68hc11/68l11 microcontroller. the microcontroller is configured as the master by setting bit mstr in the spcr to 1, which provides a serial clock on sck while the mosi output drives the serial data line sdata. because the microcontroller does not have a dedicated frame sync pin, the fsync signal is derived from a port line (pc7). the setup conditions for correct operation of the interface are as follows: sck idles high between write operations ( cpol = 0), and data is valid on sck falling edge (cpha = 1). when data is transmitted to the ad9832, the fsync line is taken low (pc7). serial data from the 68hc11/68l11 is transmitted in 8 - bit bytes with only 8 falling clock edges occurring in the transmi t cycle. data is transmitted msb first. t o load data into the ad9832, pc7 is held low after the first 8 bits are transferred and a second serial write operation is performed to the ad9832. only after the second 8 bits have been transferred should fsync be taken high again. ad9832* fsync sdata sclk 68hc11/68l11* pc7 mosi sck *additional pins omitted for clarity. 09090-029 figure 29 . 68hc11/68l11 to ad9832 interface ad9832 to 80c51/80l5 1 interface figure 30 shows the serial interface between the ad9832 and the 80c51/80l51 microcontroller. the microcontrol ler operate s in mode 0 so that txd of the 80c51/80l51 drives sclk of the ad9832 , while rxd drives the serial data line sdata. the fsync signal is again derived from a bit programmable pin on the port (p3.3 being used in the diagram). when data is transmitt ed to the ad9832, p3.3 is taken low. the 80c51/80l51 transmits data in 8 - bit bytes ; therefore, only 8 falling sclk edges occur in each cycle. to load the remaining 8 bits to the ad9832, p3.3 is held low after the first 8 bits have been transmitted and a se cond write operation is initiated to transmit the second byte of data. p3.3 is taken high following the completion of the second write operation. sclk should idle high between the two write operations. the 80c51/80l51 outputs the serial data in a format th at has lsb first . the ad9832 accepts msb first (the 4 msbs being the control information, the next 4 bits being the address , while the 8 lsbs contain the data when writing to a destination register). therefore, the transmit routine of the 80c51/80l51 must consider this format and rearrange the bits so that the msb is output first. ad9832* fsync sdata sclk 80c51/80l51* p3.3 rxd txd *additional pins omitted for clarity. 09090-030 figure 30 . 80c51/80l51 to ad9832 interface ad9832 to dsp56002 i nterface figure 31 shows the interface between the ad9832 and t he dsp56002. the dsp56002 is configured for normal mode asynchronous operation with a gated internal clock (syn = 0, gck = 1, sckd = 1). the frame sync pin is generated internally (sc2 = 1), the transfers are 16 - bits wide (wl1 = 1, wl0 = 0) , and the frame sync signal frame s the 16 bits (fsl = 0). the frame sync signal is available on pin sc2, but it needs to be inverted before being applied to the ad9832. the interface t o the dsp56000/dsp56001 is similar to that of the dsp56002. ad9832* fsync sdata sclk dsp56002* sc2 std sck *additional pins omitted for clarity. 09090-031 figure 31 . ad9832 to dsp56002 interface
data sheet ad9832 rev. e | pa ge 21 of 28 evaluation board system de monstration platform the system de monstration platform (sdp) is a hardware and software evaluation tool for use in conjunction with product evaluation boards. the sdp board is based on th e black fin ? bf527 processor with usb connectivity to the pc through a usb 2.0 high speed port. note that the sdp board is sold separately from the ad9832 evaluation board. ad9832 to sport interface the analog devices sdp board has a sport serial port that is used to control the serial inputs to the ad9832. the connections are shown in figure 32. ad 983 2 f sy n c s da t a s c l k 02705 - 0 39 sp o r t _ tf s sp o r t _ t s c l k sp o r t _ d t o ad sp - b f 52 7 figure 32 . sdp to ad9832 interface the ad9832 evaluation board allows designers to evaluate the high performance ad9832 dds modulator with a minimum of effort. the gui interface for the ad9832 evaluation board is shown in figure 33. 09090-040 figure 33 . ad9832 evaluation software the dds evaluation kit includes a populated, tested ad9832 pcb . software is available with the evaluation board that allows the user to easily program the ad9832 . the schematics of the ad9832 evaluation board are sh own in figure 34 and figure 35. the software runs on any ibm - compatible pc that has microsoft? windows? 95, windows 98, windows me, windows 2000 nt? , or windows 7 installed . additional details can be found in the eval - ad9832 sdz data sheet that is available on the software cd and on the ad9832 product page. xo vs . external clock the ad9832 can operate with master clocks up to 2 5 mhz. a 2 5 mhz general oscillator is included on the evaluation board. however, this oscillator can be removed and, if required, an external cmos clock can be connected to the part. two options for the general oscillator are ? ael 3 01 series crystals oscillators ( ael crystals, ltd. ) ? sg- 310scn oscillato rs ( epson toyocom corporation ) power supply power to the ad9832 evaluation board can be provided from a usb connector or externally through pin connections. the power leads should be twisted to reduce ground loops.
ad9832 data sheet rev. e | page 22 of 28 evaluation board sch ematics 09090-034 figure 34 . ad9832 evaluation board schematic , part a
data sheet ad9832 rev. e | page 23 of 28 09090-035 figure 35 . ad9832 evaluation board schematic , part b j1 header connector
ad9832 data sheet rev. e | page 24 of 28 evaluation board lay out 09090-036 figure 36 . ad9832 evaluation bo ard component side 09090-037 figure 37 . ad9832 evaluation board silkscreen 09090-038 figure 38 . ad9832 evaluation board solder side
data sheet ad9832 rev. e | page 25 of 28 ordering information bill of materials table 14. reference de signator description manufacturer part number c1, c 3 , c5, c6, c11, c12, c 13 0.1 f, 10%, 50 v, x7r, ceramic capacitor murata grm188r71h104ka93d c 7 0.01 f, 10%, 10 v, 0603, x5r, capacitor kemet c0603c103k5ractu c 2 , c 4 10 f, 10%,10 v, smd tantalum ca pacitor avx taja106k010r c 8,c9 1 f, 10%,10 v,y5v, 0603, ceramic capacitor yageo cc0603zry5v6bb105 c1 0 0.1 f, 10%, 16 v, x7r, 0603, capacitor multicomp b0603r104kct clk 1 , fsel 1 , iout, psel1 1 , refin, psel 0 1 straight pcb mount smb j ack, 50 ? tyco 1 - 1337482-0 fsync , iout_, mclk , sclk, sdata red test point vero 20- 313137 g 2 copper short not applicable not applicable j1 120- way connector, 0.6 mm pitch receptacle hrs (hirose) fx8 - 120s - sv(21) j2, j3 2 - pin terminal block (5 mm pitch) campden ctb5000/2 lk 3, lk5 , lk 6 3 - pin sil header and shorting link harwin m20 - 9990345 and m7567 - 05 lk 1 2 - pin sil header and shorting link harwin m20 - 9990246 r 7 1 , r 8 1 , r 9 1 10 k?, 1%, 0603, smd resistor multicomp mc 0.063w 0603 10k r 12 1 50 ?, 1%, 0603, smd resistor multicomp mc 0.063w 0603 50r r 1 4 3.9 k?, 1%, smd resistor multicomp mc 0.063w 0603 6k8 r15 3 00 ?, 1%, smd resistor multicomp mc 0.063w 0603 200r r 1 7 ,r18 100 k ?, 1%, smd resistor multicomp mc 0.063w 0603 1% 100k r 1 , r 2 1 , r 3 , r 4 1 , r 6 1 , r 5 , r1 1 1 , r1 0,r16 2 0 ?, 1%, 0603, smd resistor multicomp mc 0.063w 0603 0r r1 3 330 k?, 5%, smd resistor multicomp mc 0.063w 0603 330kr u4 45 mw power, 3 v to 5.5 v, 25 mhz complete dds analog devices ad983 2 bruz u 1 32k i 2 c serial eeprom 8 - lead mso p micro chip 24lc 32a - i/ms u 5 high accuracy anycap? 100 ma low dropout linear regulator analog devices adp3301arz - 3.3 y 2 2 5 mhz, 3 mm 2 mm smd clock oscillator ael crystals ael301 series 1 do not install. 2 dnp
ad9832 data sheet rev. e | page 26 of 28 outline dimensions 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bsc 5.10 5.00 4.90 0.65 bsc 0.15 0.05 1.20 max 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarity 0.10 compliant to jedec standards mo-153-ab figure 39 . 16 - lead thin shrink small outline package [ tssop ] (ru - 16) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD9832BRU ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 AD9832BRU - reel7 ? 40c to +85c 16- lead th in shrink small outline package [tssop] ru -16 AD9832BRUz ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 AD9832BRUz - reel ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 AD9832BRUz - reel7 ? 40c to +85c 16- lead thin shrink small outline package [tssop] ru -16 eval - ad9832sdz evaluation board 1 z = rohs compliant part.
data sheet ad9832 rev. e | page 27 of 28 notes
ad9832 data sheet rev. e | page 28 of 28 notes ? 1999 C 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d09090 - 0 - 2/13(e)

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